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    ---
    # Open Source Hardware Synthesis Tools

    Yue Tao
    
    Institute of Software, CAS

    ---

    # Logic Synthesis 

      - .bright[Code -> IR ]
        - Apply Preprocess
        - Identify **synthesizable part**
        - Produces IR
      - .bright[IR: Behavioral -> RTL] 
        - register based comb. & trans. repr. 
        - symbolic optim. / verif. applied
      - .bright[RTL -> Gate Level] 
        - all regs eliminated, gate & wire remained
        - lowest level repr.
        - graph optim. / verif. applied
      - .bright[Gate Level -> code]

    Note: 
      - A consistent memory model is required. 

    ---

    # Code -> IR

    |Language              | Based on   | purpose     | Link |
    |----------------------|------------|-------------|------|
    |ACT                   | N/A        | edu         |[ACT](https://github.com/asyncvlsi/act)|


    ---

    # Physical Synthesis

      - Code ->  
      
    ---

    # Refs:

    [1] [Verilog Formal Verification Tutorial, Gisselquist](https://zipcpu.com/tutorial/class-verilog.pdf) 

    [2] [Formal Verification with Chisel, Laeufer](https://woset-workshop.github.io/PDFs/2021/a03-slides.pdf)

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